Anvil: A General-Purpose Timing-Safe Hardware Description Language
5/9/2025, 3:00pm
Speaker
Abstract
Expressing hardware designs using hardware description languages (HDLs) routinely involves using stateless signals whose values change according to their underlying registers. Unintended behaviours can arise when the stored values in these underlying registers are mutated while their dependent signals are expected to remain constant across multiple cycles. Such timing hazards are common because existing HDLs lack abstractions for values that remain unchanged over multiple clock cycles, delegating this responsibility to hardware designers. In this talk, I present Anvil, an HDL equipped with a type system that statically guarantees timing safety, i.e., absence of timing hazards, while maintaining expressiveness for cycle-level timing control or dynamic timing behaviours. In particular, I will focus on two main aspects: 1) safety: formal definition of the timing safety property and Anvil's semantics and type system, and 2) expressiveness: empirical evaluation of Anvil's expressiveness in real-world hardware designs.
Bio
Jason Yu is a final-year PhD student at School of Computing, National University of Singapore, advised by Prateek Saxena. His research interests include systems security, computer architectures, and programming languages.